verilog.stx verilog syntax

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#Keyword1=
always
and
assign
begin
buf
bufif0
bufif1
case
casex
casez
cmos
deassign
default
defparam
disable
edge
else
end
endcase
endmodule
endfunction
endprimitive
endspecify
endtable
endtask
event
for
force
forever
fork
function
highz0
highz1
if
initial
inout
input
integer
join
large
Library
macromodule
medium
module
nand
negedge
nmos
nor
not
notif0
notif1
or
output
parameter
pmos
posedge
primitive
pull0
pull1
pullup
pulldown
rcmos
reg
release
repeat
rnmos
rpmos
rtran
rtranif0
rtanif1
scalared
small
specify
specparam
strength
strong0
strong1
supply0
supply1
table
task
time
tran
tranif0
tranif1
tri1
tri0
triand
trior
trireg
vectored
wait
wand
weak0
weak1
while
wire
wor
xnor
xor
#Keyword2=
$bitstoreal
$countdrivers
$display
$fclose
$fdisplay
$finish
$fmonitor
$fopen
$fstrobe
$fwrite
$finish
$getpattern
$history
$hold
$incsave
$input
$itor
$key
$list
$log
$monitor
$monitoroff
$monitoron
$nokey
$nolog
$period
$printtimescale
$readmemb
$readmemh
$realtime
$realtobits
$recovery
$reset
$reset_count
$reset_value
$restart
$rtoi
$save
$scale
$scope
$setup
$setuphold
$showscopes
$showvariables
$showvars
$skew
$sreadmemb
$sreadmemh
$stime
$stop
$strobe
$time
$timeformat
$width
$write
#Keyword3=
`accelerate
`autoexepand_vectornets
`celldefine
`default_nettype
`define
`else
`endcelldefine
`endif
`endprotect
`endprotected
`expand_vectornets
`ifdef
`include
`noaccelerate
`noexpand_vectornets
`noremove_gatenames
`noremove_netnames
`nounconnected_drive
`protect
`protected
`remove_gatenames
`remove_netnames
`resetall
`timescale
`unconnected_drive
accelerate
autoexepand_vectornets
celldefine
default_nettype
define
endcelldefine
endif
endprotect
endprotected
expand_vectornets
ifdef
include
noaccelerate
noexpand_vectornets
noremove_gatenames
noremove_netnames
nounconnected_drive
protect protected
remove_gatenames
remove_netnames
resetall
timescale
unconnected_drive
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#Operator=
`
{
}
+
-
*
/
%
>
>=
>>
<
<=
<<
!
!=
!==
&
&&
|
||
==
===
^
^~
~
~^
~&
~|
?
:
#
@

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#SyntaxName=Verilog